Many communications and radar systems require radio frequency (RF) synthesizer performance, which often can be difficult to implement using direct frequency multiplication, phase-locked-loop (PLL), or direct digital synthesizer (DDS) techniques. To achieve characteristics of a desired frequency range, a high frequency output, a fine tuning resolution, a fast settling time, and a low phase noise, system designers often combine PLL and DDS technologies. The strengths of one technology join with strengths of the other technology to extend a possible range of performance.
As one example, a PLL, also known as Indirect synthesis, is a negative feedback loop structure that locks a phase of an output signal after division to a reference clock. Thus, the output signal of the PLL has a phase related to a phase of the input reference signal. For example, the PLL compares a phase of an input signal with a phase signal derived from its output oscillator signal and adjusts a frequency of its oscillator to keep the phases matched. A PLL may include a variable counter (divider) to allow generation of many frequencies by changing a division ratio.
As another example, DDS is a technique for using digital data processing blocks to generate a frequency and phase-tunable output signal referenced to a fixed-frequency clock source. The reference clock frequency is divided down in a DDS architecture by a scaling factor set forth in a programmable binary tuning word. The tuning word is typically 24-48 bits long which enables a DDS implementation to provide high output frequency tuning resolution.
DDS technologies may be used to achieve fast switching (typically less than a microsecond), which can be important in spread-spectrum or frequency-hopping systems including radar and communication systems. Additional advantages of DDS technologies include fine tuning steps, low phase noise, transient-free (phase continuous) frequency changes, flexibility as a modulator, and small size, among others.
However, DDS systems may have an operating range that is limited by the Shannon, Nyquist sampling theory. For example, an output is typically limited to about 45% of a maximum clock rate at which the DDS can be operated. Another limitation of DDS systems may include spectral purity, which is governed by a density/complexity of the DDS circuitry that is attainable at a desired operating speed.